1. Field of the Invention
The present invention relates to a print head of the dynamically driven type, and an image forming apparatus employing the print head.
2. Description of the Related Art
The present invention is applicable to, for example, an electrophotographic printer in which a charged photosensitive drum is selectively illuminated to form an electrostatic latent image, which is developed by application of toner, then transferred to paper and fused onto the paper. To understand the problem addressed by the present invention, it is useful to understand the control circuits of this type of printer in some detail, so a description will be given at this point with reference to FIG. 1, which is a block diagram of the control circuits of an electrophotographic printer employing light-emitting diodes (LEDs) for illumination, and FIGS. 2 and 3, which are timing diagrams illustrating the printing operation.
The printing control unit 1 in FIG. 1 is a computing device comprising a microprocessor, read-only memory (ROM), random-access memory (RAM), input-output ports, timers, and other facilities. Upon receiving signals SG1, SG2, etc. from a higher-order controller (not visible), the printing control unit 1 generates signals that control a sequence of operations for printing dot-mapped data. The data are provided in signal SG2, which is sometimes referred to as a video signal because it supplies the dot-mapped data one-dimensionally.
The printing sequence starts when the printing control unit 1 receives a printing command from the higher-order controller by means of control signal SG1. First, a temperature (Temp.) sensor 160 is checked to determine whether the fuser 161 is at the necessary temperature for printing. If it is not, current is fed to a heater 161a to raise the temperature of the fuser 161.
When the fuser 161 is ready, the printing control unit 1 commands a motor driver 162 to drive a develop-transfer process motor (PM) 163, activates a charge signal SGC to turn on a charging power source 164, and thereby applies a voltage to a charging unit 165 that negatively charges the surface of a photosensitive drum (not visible).
In addition, a paper sensor 166 is checked to confirm that paper is present in a cassette (not visible), and a size sensor 167 is checked to determine the size of the paper. If paper is present, another motor driver 168 drives a paper transport motor (PM) 169 according to the size of the paper, first in one direction to transport the paper to a starting position sensed by a pick-up sensor 170, then in the opposite direction to transport the paper into the printing mechanism.
When the paper is in position for printing, the printing control unit 1 sends the higher-order controller a timing signal SG3 (including a main scanning synchronization signal and a sub-scanning synchronization signal) as shown in FIG. 2. The higher-order controller responds by sending the dot data for one page in the video signal SG2. The printing control unit 1 sends corresponding dot data (HD-DATA) to an LED head 2 in synchronization with a clock signal (HD-CLK). The LED head 2 comprises a linear array of LEDs for printing respective dots.
After receiving data for one line of dots in the video signal SG2 and sending the data to the LED head 2, the printing control unit 1 sends the LED head 2 a latch command by means of a load signal (HD-LOAD), causing the LED head 2 to store the print data (HD-DATA), then sends the LED head 2 a strobe signal (HD-STB-N), causing the LED head 2 to illuminate the negatively-charged photosensitive drum according to the stored print data (HD-DATA), thereby forming an electrostatic latent image made up of dots with higher potentials than their surrounding areas. In the developer (not shown), negatively charged toner particles are electrically attracted to these dots, so that a toner image is formed. FIG. 2 illustrates these operations for three consecutive lines (lines Nxe2x88x921, N, N+1).
FIG. 3 shows the above sequence of signals in more detail, assuming that there are four thousand nine hundred ninety-two (4992) dots per line, which is suitable for printing six hundred dots per inch (600 dpi) on A4-size paper. To speed up the printing process, the strobing of one line (e.g., line Nxe2x88x921) may proceed in parallel with the transfer of data for the next line (e.g., line N), and the fastest possible clock rate may also be used.
Rotation of the photosensitive drum brings the toner image to a transfer unit 171. A high-voltage transfer power source 172 turned on by control signal SG4 supplies a positive voltage to the transfer unit 171, whereby the toner image is transferred onto paper as the paper passes between the photosensitive drum and the transfer unit.
The paper bearing the transferred toner image is transported to the fuser 161. When the paper meets the fuser 161, the toner image is fused onto the paper by a combination of pressure and heat generated by the heater 161a. Finally, the printed sheet of paper passes an exit sensor 173 and is ejected from the printer.
The printing control unit 1 controls the high-voltage transfer power source 172 according to the information detected by the size sensor 167 and pick-up sensor 170 so that voltage is applied to the transfer unit 171 only while paper is passing between the transfer unit 171 and photosensitive drum. When the paper passes the exit sensor 173, the printing control unit 1 turns off the high-voltage charging power source 164 and halts the developer-transfer process motor 163.
When a series of pages are printed, the above operations are repeated.
FIG. 4 is a simplified schematic drawing showing the conventional circuit structure of the LED head 2. The print data signal HD-DATA and clock signal HD-CLK are received by a shift register comprising, for example, four thousand nine hundred ninety-two flip-flops FF1, FF2, . . . , FF4992. The load signal HD-LOAD is received by a corresponding number of latches LT1, LT2, . . . , LT4992, which latch the data output by the shift-register flip-flops when the HD-LOAD signal is active (high). The strobe signal HD-STB-N is supplied to a circuit comprising an inverter G0, NAND gates G1, G2, . . . , G4992, and switching elements (transistors) TR1, TR2, . . . , TR4992 which are interconnected to drive a linear array of light-emitting diodes LD1, LD2, . . . , LD4992 when the strobe signal HD-STB-N is active (low), provided the print data output from the corresponding latches are high (indicating black dots). The transistors TR1, TR2, . . . , TR4992 operate as an array of driving elements, while the LEDs LD1, LD2, . . . , LD4992 operate as an array of driven elements. The power source of the current that drives the LEDs is denoted VDD.
The output signals from the latches are also supplied to a plurality of memory circuits M1, M2, . . . , M4992 that store compensation data for the LEDs. Several bits of compensation data (b0-b5) are output for each LED. These bits control further transistors that supply additional current to the LEDs LD1, LD2, . . . , LD4992 to compensate for LED-to-LED variations in the electrical characteristics of the LEDs themselves and their main driving transistors TR1, TR2, . . . , TR4992.
Incidentally, in the flip-flops FF1, FF2, . . . in FIG. 4, D1, D2, . . . are data input terminals and Q1, Q2, . . . are data output terminals. In the latches LT1, LT2, . . . , D is a data input terminal, Q is a data output terminal, and G is a control signal input terminal.
The memory compensation data circuits M1, M2, . . . , M4992 are necessary for the following reason. In a printer employing the LED head in FIG. 4, all of the LEDs LD1, LD2, . . . , LD4992 are switched on for the same length of time, which is determined by the strobe signal HD-STB-N. Thus if these LEDs, or their driving transistors TR1, TR2, . . . , TR4992, do not have perfectly uniform electrical properties, different dots will receive different amounts of optical energy. This leads to differences in the sizes of the electrostatic dots in the latent image formed on the photosensitive drum, hence to differences in the sizes of the dots printed on the page.
Typical differences in LED output are illustrated by the graph in FIG. 5. Dot position is indicated on the horizontal axis, and optical power on the vertical axis. The light-emitting diodes are disposed in a plurality of semiconductor chips, more specifically LED array chips denoted CHIP1 to CHIP26, which are driven by a like plurality of integrated driver circuits (driver ICs) DRV1 to DRV26, as illustrated at the top of FIG. 5. One hundred ninety-two LEDs are integrated in each LED array chip. The LED array chips and driver ICs are interconnected by wire bonding. The driver ICs are cascaded to form a single shift register for receiving the dot data signal HD-DATA.
The horizontal dotted lines indicate the ranges of variability of the optical power output by the LEDs in each individual LED array. The horizontal dot-dash lines indicate the range of variability of the average optical output power of the different LED arrays. Thus the dotted lines indicate ranges A of dot-to-dot variation within each array, while the dot-dash lines indicate the range B of chip-to-chip variation.
As illustrated in FIG. 5, the range B of chip-to-chip variation is much greater than the range A of dot-to-dot variation within any one chip. One conventional practice has therefore been to grade the driver IC chips and LED array chips according to their average output power, and assemble each LED head from chips of the same grade. Alternatively, the average current that must be supplied to each LED array chip to obtain a nominal average optical output can be calculated from measurements of the LED array chips, the average current supplied by each driver IC can be measured, the driver IC chips can be graded according to their average current output, and each LED array chip can be paired with a driver IC that supplies substantially the right amount of average current. In this way it is possible to reduce chip-to-chip differences, but the dot-to-dot differences within each chip remain uncorrected. Although different dot sizes are not readily noticeable on pages containing only line art or text, when photographs or similar types of images are printed, variations in dot size create density differences that can degrade the printing quality to an undesirable degree.
To compensate for such differences, compensation data are determined by measuring the output of each LED when the LED head is manufactured. The compensation data are, for example, stored in a non-volatile memory in the printing control unit and transferred to the data compensation memory circuits M1, M2, . . . , M4992 before printing begins. During printing, when transistor TR1, for example, is turned on to drive LED LD1, one or more additional transistors controlled by bits output from data compensation memory circuit M1 may also be turned on. The current driving capability of these additional transistors is weighted in a doubling ratio (1:2:4:8 . . . ), providing 2n different levels of additional current, where n is the number of compensation bits per LED.
When the spacing of the LEDs becomes as small as {fraction (1/600)} inch, however if an LED array chip has a separate bonding pad for each LED, then bonding wires must also be bonded at intervals of {fraction (1/600)} inch, which is difficult, time-consuming, and expensive. The wire-bonding requirements can be reduced by a known dynamic driving scheme.
FIG. 6 illustrates an LED array chip in an LED head that employs dynamic driving. The corresponding driver IC (not visible) supplies current to anode input pads 185-188, each of which is connected to the anodes two adjacent LEDs in the array of LEDs 189-196. For example, mutually adjacent LEDs 189 and 190 are both connected by anode wiring 212 to anode input pad 185. The other adjacent pairs of LEDs are connected by other anode wiring 213-215 to the other anode input pads 186-188. The cathode terminals of the LEDs are coupled alternately to two cathode input pads 197, 198. The cathodes of all of the odd-numbered LEDs 189, 191, . . . , 195 are connected by cathode wiring to cathode input pad 197; the cathodes of all of the even-numbered LEDs 190, 192, . . . , 196 are connected by cathode wiring to cathode input pad 198.
LED 189 is driven by placing anode input pad 185 at the high (VDD) logic level and cathode input pad 197 at the low (ground) logic level. Other LEDs 191, 193, 195 connected to cathode input pad 197 may also be driven at this time, by driving their anode input pads 186, 187, 188 to the high logic level, or they may be left off, by leaving their anode input pads 186, 187, 188 at the low logic level. To avoid unwanted driving of LEDs 190, 192, 193, 196, cathode input pad 198 is placed at the high logic level. After the odd-numbered LEDs 189, 191, . . . , 195 have been driven in this way, the even-numbered LEDs 189, 191, . . . , 195 are similarly driven by placing cathode input pad 197 at the high logic level and cathode input pad 198 at the low logic level.
This dynamic driving scheme reduces the cost of the LED head by reducing the number of bonding wires and the amount of driving circuitry needed to drive the LED array chips. It also lengthens the life of the LED head by reducing the amount of heat generated at any one time.
Since the driving current for two LEDs is supplied to the same anode input terminal, however, the circuit that supplies the current must be multiplexed. FIG. 7 shows a one-bit multiplexer comprising a pair of complementary metal-oxide-semiconductor (CMOS) AND gates 199, 200 and a CMOS OR gate 201. Input A is passed to output Y when selection signal SA is high; input B is passed to output Y when selection signal SB is high. Each logic gate 199, 200, 201 includes six transistors, so this multiplexer requires a total of eighteen transistors.
FIG. 8 illustrates the operation of the multiplexer in FIG. 7. As indicated by the arrows, the output Y is high when A and SA are both high, or B and SB are both high, and is low at other times.
FIG. 9 illustrates another type of multiplexer in which n-channel metal-oxide-semiconductor (NMOS) transistors 202, 203 are paired with p-channel metal-oxide-semiconductor (PMOS) transistors 204, 205 to form two transmission gates controlled by respective selection signals SA and SB. This multiplexer also includes CMOS inverters 206, 207, 208, 209, 210 that buffer the input and output signals and invert the selection signals for control of the PMOS transistors. Each CMOS inverter includes two transistors, so the total number of transistors in this multiplexer is fourteen.
The multiplexer in FIG. 9 operates as illustrated in FIG. 10. The output Y goes high when A and SA, or B and SB, are both high, and remains high until SA or SB goes high while the corresponding input (A or B) is low. The reason for the sustained high output is that when signals SA and SB are both low, the transmission gate transistors 202, 203, 204, 205 in FIG. 9 are all switched off, and inverter 210 cannot receive the high input signal that would be needed to produce a low output signal Y.
Since one multiplexer of the type shown in FIG. 7 or 9 is needed for each anode input pad in FIG. 6, the multiplexers occupy a significant amount of space in the driver ICs. To save space, it would be desirable to reduce the number of transistors in these multiplexers. In FIG. 7, the necessary number of transistors can be reduced from eighteen to twelve by using CMOS NAND gates instead of AND and OR gates.
In FIG. 9, however, all of the transistors shown are necessary, for the following reason. When the output of inverter 206 is high, NMOS transistor 202 cannot transmit the full high output potential of inverter 206 to inverter 210, even when the SA signal is high, due to an inadequate gate-source potential difference. Similarly, when the output of inverter 206 is low, PMOS transistor 204 cannot transmit the full low output potential of inverter 206 to inverter 210. Thus NMOS transistor is needed to transmit the low logic level to inverter 210, PMOS transistor 204 is needed to transmit the high logic level to inverter 210, and inverter 207 is needed to control PMOS transistor 204. Similarly, NMOS transistor 203, PMOS transistor 205, and inverter 209 are all needed in order to transmit the full output levels of inverter 208 to inverter 210.
The conventional multiplexers thus require at least twelve transistors (FIG. 7) or fourteen transistors (FIG. 9) per output bit.
Another problem encountered in dynamic driving is that since two (or more) LEDs are driven from the same anode input pad, compensation data cannot be stored in memory circuits in the driver ICs in the LED head as illustrated in FIG. 4. Instead, the compensation data are conventionally supplied to the driver ICs together with the print data, but this slows down the printing process.
A similar problem arises when dynamic driving is used in the print head of a thermal printer, which has heat-emitting elements requiring similar compensation.
An object of the present invention is to provide a print head that uses dynamic driving and stores compensation data for individual driven elements.
Another object of the invention is to reduce the amount of compensation data that must be stored in the print head.
Another object is to multiplex the compensation data efficiently.
The invented print head includes a row of driven elements that are connected to a plurality of first terminals and a plurality of second terminals, and driver circuitry that drives the driven elements by driving the first and second terminals. Each driven element is driven by driving a different combination of one of the first terminals and one of the second terminals. The print head also includes means for storing compensation data specifying amounts of energy to be supplied by the driver circuitry to the first terminals, and means for selecting the stored compensation data according to the combination of the first terminals and the second terminals driven by the driver circuitry. The selected compensation data are supplied to the driver circuitry. Typically, the driver circuitry drives the second terminals one at a time, and the means for selecting selects the compensation data according to the second terminal that is driven. The means for selecting enables the compensation data to be stored in the print head despite the use of dynamic driving by the driver circuitry.
The means for storing compensation data may include a first memory circuit storing common compensation data for all of the driven elements connected to one of the first terminals, and a plurality of second memory circuits storing individual compensation data for individual ones of these driven elements. Typically, the common compensation data are more significant than the individual compensation data; that is, the common compensation data include the more significant bits. By sharing part of the compensation data, this storage scheme reduces the amount of compensation data that has to be stored.
The means for selecting preferably employs a type of multiplexer in which a metal-oxide-semiconductor transistor of one channel type is connected to a plurality of metal-oxide-semiconductor transistors of the opposite channel type. Just one of these transistors is switched on at a time, either to supply a bit of compensation data, or to precharge a node to the power-supply potential or the ground potential. This circuit multiplexes data efficiently with a comparatively small number of transistors.
The driven elements may be, for example, light-emitting elements or heat-emitting elements.
The invention also provides an image-forming device including the invented print head and a printing control unit that transfers the compensation data to the print head.